Electronic chips may contain both logic circuits and phase-change memory circuits. Logic circuits comprise many MOS-type transistors. Memory circuits include memory cells arranged in an array, and each memory cell is associated with a vertical bipolar transistor. Such a transistor is used to independently program, erase or read each memory cell. The bipolar transistors corresponding to the memory cells of a same row of the array have a common base. The memory cells of a same column of the array are arranged between the emitter of the corresponding bipolar transistor and a common upper metallization. When it is desired to program, erase, or read a memory cell, the bipolar transistors of the corresponding rows are turned on and a voltage is applied to the upper metallization of the corresponding column. A memory cell programming, erasing, or reading current is thus circulated in the memory cell.
Conventional methods have been provided to form in a portion of a chip, complementary MOS transistors and, in another portion of the chip, vertical bipolar transistors controllable by a common base. Such methods raise various implementation issues.
There is a need for a method which is simple and compatible with a conventional CMOS technology, enabling to form at the same time complementary MOS transistors and bipolar transistors having a common base.